XCR3064XL-10VQG100C, Xilinx

XCR3064XL-10VQG100C, Xilinx

The CoolRunner™ XPLA3 XCR3064XL device is a 3.3V,
64-macrocell CPLD targeted at power sensitive designs
that require leading edge programmable logic solutions. A
total of four function blocks provide 1,500 usable gates.
Pin-to-pin propagation delays are as fast as 5.5 ns with a
maximum system frequency of 192 MHz.
TotalCMOS Design Technique for Fast
Zero Power
CoolRunner XPLA3 CPLDs offer a TotalCMOS solution,
both in process technology and design technique. Xilinx
employs a cascade of CMOS gates to implement its sum of
products instead of the traditional sense amp approach.
This CMOS gate implementation allows Xilinx to offer
CPLDs that are both high performance and low power,
breaking the paradigm that to have low power, you must
have low performance. Refer to Figure 1 and Table 1

showing the ICC vs. Frequency of our XCR3064XL TotalCMOS
CPLD (data taken with four resetable up/down, 16-bit
counters at 3.3V, 25° C).